1. Field of the Invention
The present invention generally relates to memory devices, and more particularly, the present invention relates to a voltage generation circuit of a flash memory device, a flash memory device including a voltage generation circuit, and a method of programming a flash memory device.
A claim of priority under 35 USC § 119 is made to Korean Patent Application No. 10-2006-0099156, filed Oct. 12, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
An EEPROM (Electrically Erasable and Programmable ROM) is a type of non-volatile memory device which retains stored data in the absence of supplied power. Generally, an EEPROM operates in one of three modes, namely, a program mode for writing data to a memory cell, a read mode for reading stored data, and an erase mode for erasing the stored data.
A flash memory device is an EEPROM which is characterized by simultaneously executing an erase operation in units of memory blocks or memory sectors. Depending on its memory cell array structure, a flash memory devices may be either a NAND type flash memory device or a NOR type flash memory device. In a NAND type flash memory device, cell transistors are connected to each other in series between a bit line and a ground electrode. In a NOR type flash memory device, cell transistors are connected in parallel between a bit line and a ground electrode. The NOR type flash memory device has the advantage of random data access by performing a read operation and a program operation per byte, but has the disadvantage of slow programming and erase speeds when compared with the NAND type flash memory device.
FIG. 1 is a simplified block diagram illustrating a conventional flash memory device.
Referring to FIG. 1, the flash memory device includes a memory cell array 10, a row selection circuit 20, a column selection circuit 30 and a write driver 40.
The memory cell array 10 includes memory cells such as cell transistors, which are respectively coupled to one of a plurality of word lines and to one of a plurality of bit lines. Among a plurality of cell transistors included in the NOR type memory cell array 10, only a single cell transistor 11 selected to be programmed is illustrated in FIG. 1.
The row selection circuit 20 decodes a row address signal ADDX and selects a word line 12 coupled to the cell transistor 11 to be programmed. A word line program voltage VPW is applied to a control gate of the cell transistor through the selected word line 12. Electrons are injected into a floating gate due to the high voltage applied to the control gate so that a selected cell is programmed.
In the program mode of the NOR type flash memory, for example, the program operation is performed by applying a high voltage not less than about 4V to the bit line and applying a high voltage of about 10V to the word line. For example, both of the high voltages may be generated by a charge pump. In a typical NOR type flash memory device, the program operation is performed when the two high voltages generated by the charge pump reach a target maximum value.
As shown in FIG. 1, the column selection circuit 30 may include a local column decoder 31, a global column decoder 32, level shifters 33 and 34 and selection transistors 35 and 36. The column selection circuit 30 decodes a column address ADDY and selects a bit line 13 including the cell transistor 11 to be programmed.
Typically, bit lines of memory devices have a hierarchical structure including a local bit line coupled to a predetermined number of memory cells and a global bit line coupled in common to a plurality of the local bit lines. Only a single local bit line 13 and a single global bit line 14, which are selected, are shown in FIG. 1. The bit line may be selected by switching operations of the local bit line selection transistor 35 and the global bit line selection transistor 36. The column decoders 31 and 32 decode the column address signal ADDY and output selection signals for selecting a bit line. The level shifters 33 and 34 increase a voltage level of the selection signals to a column selection voltage VPPY that is provided as a gate voltage of the bit line selection transistors 35 and 36.
The write driver 40 receives program data DQ, and increases a voltage level of the program data DQ by a bit line program voltage VPB and then outputs the voltage-increased program data DQ to the column selection circuit 30. In the flash memory device, a high voltage is applied to the bit line in the program operation. Particularly, in the NOR type flash memory device, a bit line program voltage not less than about 4V is needed when a word line program voltage is about 10V in order to perform the program operation by channel hot electron (CHE) injection. In order to transfer this high voltage from the write driver 40 to the selected local bit line without loss, high voltage should be applied to the gates of the selection transistors 35 and 36 on the path. Accordingly, the column selection voltage VPPY should be greater than a certain voltage level so that the level shifters 33 and 34 may output a sufficiently high gate voltage.
FIG. 2 is a block diagram illustrating a conventional voltage generation circuit of a flash memory device.
Referring to FIG. 2, the voltage generation circuit 100 of the flash memory device includes a high voltage generator 110, a word line voltage regulator 120 and a column selection voltage switch 130.
The high voltage generator 110 generates and outputs a high voltage VPI based on a power voltage, and generates the high voltage setup signal SUVPI representing that the high voltage VPI is set up to a maximum value. A charge pump may be included in the high voltage generator 110 as a means for increasing a voltage.
A word line voltage regulator 120 receives the high voltage VPI from the high voltage generator 110 and generates an incremental step pulse. The word line voltage regulator 120 begins to output the incremental step pulse to the row selection circuit 20 in response to a program setup signal SUPGM. For example, a controller of the flash memory device may generate a control signal CTLREG in response to the program setup signal SUPGM, and the word line voltage regulator 120 gradually increases a voltage level of the incremental step pulse in response to the control signal CTLREG. The row selection circuit 20 in FIG. 1 outputs the received incremental step pulse as a word line program voltage VPW to the selected word line.
As mentioned above, the word line voltage regulator 120 performs a program operation by using an incremental step pulse programming (ISPP) scheme in which a gradually increasing voltage is used as a word line program voltage.
The column selection voltage switch 130 receives the high voltage VPI from the high voltage generator 110 and outputs a column selection voltage for selecting a bit line. Since the column selection voltage of a high value is required in the program mode, the column selection voltage switch 130 outputs the high voltage VPI in the program mode and outputs a read column selection voltage VPRDY which is lower than the high voltage VPI in the read mode.
FIG. 3 is a timing diagram for describing an operation of the voltage generation circuit in FIG. 2.
The high voltage generator 110 starts boosting of the power voltage VDD in response to a program enable signal that is activated at time t0, and outputs the high voltage VPI. The high voltage generator 110 outputs a high voltage setup signal SUVPI that is activated when the high voltage VPI is set up to the maximum value V2 at time t2. The word line voltage regulator 120 receives the high voltage VPI from the high voltage generator 110 and generates an incremental step pulse. The word line voltage regulator 120 generates a word line voltage setup signal SUVPW that is activated when a first voltage level of the incremental step pulse is set up at time t1.
Since the column selection voltage VPPY of a high value is required in the program mode, the word line voltage regulator 120 outputs the word line program voltage VPW in the form of the incremental step pulse when the high voltage VPI used as the column selection voltage VPPY is set up to the maximum value. The voltage generation circuit 100 may include a timing control circuit 140 for triggering the output of the incremental step pulse. The timing control circuit 140 generates a program setup signal SUPGM which is activated when both the high voltage setup signal SUVPI and the word line voltage setup signal SUVPW are activated. The controller of the flash memory device may generate the control signal CTLREG in response to the program setup signal SUPGM, and the word line voltage regulator 120 may begin to gradually increase a voltage level of the incremental step pulse in response to the control signal CTLREG.
As shown in FIG. 3, the conventional voltage generation circuit 100 outputs the incremental step pulse after a delay time TD1. The delay time TD1 is needed for setting up the high voltage VPI, which is used as the column selection voltage VPPY, to the maximum value in the program mode. In this case, a program time is equivalent to a sum of the delay time TD1 and the step pulse output time TSP as shown in FIG. 3. Accordingly, the program time is increased as a result of the requirement that the column selection voltage VPPY should be greater than a certain voltage level, thereby degrading performance of the flash memory device.